The invention generally relates to a device and method to test on-chip memory in a production environment, and more specifically to ensure the proper functionality of static random access memory (SRAM) embedded in a chip in a production and post production environment.
Advances in chip manufacturing technology have enabled rapid progress to be seen in the speed, size and cost of computer systems. At one time it would have been considered impossible to put a sizable amount of memory on a single chip. Today not only is it possible to have a large amount of memory on a single chip, it is also possible for the circuitry for a device or a communications controller to be placed on a single chip and also have a significant amount of embedded memory in the form of SRAM on the same chip. In this manner a chip 10, as shown in FIG. 1, would have its own Random Access Memory (RAM) 30 that it may use as temporary storage. This chip 10 may be, for example, a cluster adapter used in a next generation input/output (NGIO) architecture and the RAM 30 may be use to store such information as a routing table that identifies the shortest path to any node in the network or as temporary storage of data being transferred from one port to another. The RAM 30 would be accessed by the chip 10 control circuitry 20 via input 60 and output 70. Chip 10 would in turn interface to other system components through input port 40 and output port 50.
By using a RAM 30 located on the same chip 10 as the control circuitry 20, it is possible to achieve an enormous performance increase over accessing a computer""s main memory to store needed tables and act as a temporary storage. This performance improvement can even be seen when memory used by a controller is on one chip and the controller is on another.
However, a significant problem arises in the manufacturing of a chip 10 that has both control circuitry 20 used for communications in a network or to perform some other function as well as having embedded RAM 30. This problem is that there is no way to directly access RAM 30 from outside the chip 10 in order to test if all bits in the RAM 30 are functioning properly at full operating speed of the chip. In a chip that has only memory on it, each and every bit may be directly accessed through the pins on the chip from a tester. In the case of the chip 10, shown in FIG. 1, no direct access method is provided to RAM 30 from outside chip 10 through input pins 40 and the reading of memory through output pins 50. Any memory access to RAM 30 is through control circuitry 20 via memory input channels 60 and memory output channel 70. However, the control circuitry 20 is not designed to test RAM 30 but to use RAM 30 to perform some other function, such as communications. This control circuitry 20 was never designed to perform memory tests.
This problem can be extremely significant to a manufacturer that warranties its products against defects. A single bit that is not functioning properly can cause severe problems which would be difficult to diagnose in a computer system. Therefore, until the creation of the present invention, only functional tests of the chip 10 were possible. None of these tests could identify a problem related to the RAM 30, let alone a problem with individual bits in the RAM 30. Further, testing memory requires checking for data retention faults to determine if a bit will hold its value over time, stuck-at faults to determine if a bit can have its value changed, and metal bridging faults in which resistive shorts between metal lines on the same layer causing a cell to read back the wrong data. In addition, further memory must be performed to check for coupling faults in which two adjacent cells or bit have the same value, address faults related to accessing memory locations, and read disturbance faults in which the value of a bit changes when it is read.
Therefore, what is needed is a device and method in which memory embedded in a chip whose primary function is not memory access may be completely tested. This device and method must have as little impact on the hardware design of the chip as possible so as not to interfere with the normal operation of the chip and to take up minimal space on the chip. This device and method should also not require a significant number of additional pins on the chip and not require additional pins to enable direct memory access to the chip.